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fujitsu semiconductor data sheet copyright?2009-2010 fujitsu semiconductor limited all rights reserved 2010.7 memory consumer fcram tm cmos 512m bit (4 bank x 2m word x 64 bit) consumer applications specific memory for sip mb81eds516545 description the fujitsu mb81eds516545 is a cmos fast cycle random access memory (fcram*) with low power double data rate (lpddr) sdram interface containing 536, 870, 912 storages accessible in a 64-bit format. mb81eds516545 is suited for consumer application requiring high data b and width with low power consumption. * : fcram is a trademark of fujit su semiconductor limited, japan features ?2 m word 64 bit 4 banks organization ? ddr burst read/write access capability -t ck = 4.6 ns min / 216 mhz max (tj + 105 c) -t ck = 5 ns min / 200 mhz max (tj + 125 c) ? low voltage power supply: v dd = v ddq + 1.7 v to + 1.9 v ? junction temperature: t j = ? 10 c to + 125 c ? 1.8 v-cmos compatible inputs ? unidirectional read data strobe per 2 byte ? unidirectional write data strobe per 2 byte ? burst length: 2, 4, 8, 16 ? cas latency: 2, 3, 4 ? clock stop capability during idle periods ? auto precharge option for each burst access ? configurable driver strength and pre driver strength ? auto refresh and self refresh modes ? deep power down mode ? low power consumption -i dd4r =330 ma max @ 3.46 gbyte/s -i dd4w =380 ma max @ 3.46 gbyte/s ? 8 k refresh cycles /16.7 ms (tj + 125 c) (continued) ds05-11463-2e
mb81eds516545 2 ds05-11463-2e (continued) ? optional commands and features -multi bank active (mact) -multi bank precharge (mpre) -background refresh (bref) -additional rdqs toggle (art)
mb81eds516545 ds05-11463-2e 3 pin descriptions *1 : dm0, dm1, dm2, dm3, dm4, dm5, dm6 and dm7 correspond to dq[7:0], dq[15:8], dq[23:16], dq[31:24], dq[39:32], dq[47:40], dq[55:48] and dq[63:56]. *2 : unidirectional data strobe per 2 byte. rd qs0/wdqs0, rdqs1/wdqs1, rdqs2/wdqs2 and rdqs3/ wdqs3 correspond to dq[15:0], dq [31:16], dq[47:32] and dq[63:48]. *3 : sa can be tied to v ss if the optional commands, multi bank active (mact), multi bank precharge (mpre) and background refr esh (bref), are not required. symbol type function ck, ck input clock cke input clock enable cs input chip select ras input row address strobe cas input column address strobe we input write enable ba[1:0] input bank address inputs a[12:0] input address inputs row a0 to a12 column a0 to a7 ap(a10) input auto precharge enable dm[7:0] * 1 input input data mask enable dq[63:0] * 1, * 2 i/o data bus input / output rdqs[3:0] * 2 output read data strobe wdqs[3:0] * 2 input write data strobe sa * 3 input select area enable v ddq , v dd supply power supply v ssq , v ss supply ground
mb81eds516545 4 ds05-11463-2e 1. clock inputs (ck and ck ) ck and ck are differential clock inputs. all address and control input signals are sampled on the rising edge of ck. and the rising edge of ck and the rising edge of ck increment device internal address counter and drive even and odd data input/out respectively. 2. clock enable (cke) cke is a high active clock enable signal. when cke = low is latched at the rising edge of ck, the next ck rising edge will be invalid. cke controls powe r down mode and self refresh mode. 3. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address inputs. cs = high disable command input but internal operation such as burst cycle will not be suspended. 4. command inputs (ras , cas and we ) the combination of ras , cas , and we input in conjunction with cs at a rising edge of the ck define the command for device operation. refer to the ? command truth table?. 5. bank address inputs (ba0, ba1) ba0 and ba1 define to which ban k an active, read, write or precharge command is being applied. ck ck t ck t ch t cl t ck t ch t cl t dc t dc ck ck cke ck (internal) t is t is
mb81eds516545 ds05-11463-2e 5 6. address inputs (a0 to a12) address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix. total 21 address input signals are required to decode such a ma trix. row address (ra) is input from a0 to a12 and column address (ca) is input from a0 to a7. row a ddresses are latched with active (act or mact) com- mands, and column addresses and auto precharge (ap) bit are latched with read (read or reada) or write command (writ or writa). ? command and address inputs setup and hold time 7. input data mask (dm0 to dm7) dm is an input mask signal for write data. input dat a is masked when dm is sa mpled high on the both edges of wdqs along with input data. dm0, dm1, dm2, dm 3, dm4, dm5, dm6 and dm7 correspond to dq[7:0], dq[15:8], dq[23:16], dq[31:24], dq[39:32], dq[47:40], dq[55:48] and dq[63:56] respectively. refer to the ?dq/rdqs/wdqs/dm correspondence table?. 8. data bus input / output (dq0 to dq63) dq is data bus input / output signal. 9. read data strobe (rdqs0 to rdqs3) rdqs is output signal transmitted by memory during read operation. rdqs is edge aligned with output data. rdqs0, rdqs1, rdqs2 and rdqs3 correspond to dq[ 15:0], dq[31:16], dq[47:32] and dq[63:48] respec- tively. refer to the ?dq/rdqs/wdqs/dm correspondence table?. after stable power supply, rdqs outputs low. ck command (cs , ras , cas , we ) t is address t ih t ipw
mb81eds516545 6 ds05-11463-2e 10. write data strobe (wdqs0 to wdqs3) wdqs is input signal transmitted by the memory controller during write operation. wd qs is center aligned with input data. wdqs0, wdqs1, wdqs2 and wdqs3 co rrespond to dq[15:0], dq[31:16], dq[47:32] and dq[63:48] respectively. refer to the ?dq/rdqs/wdqs/dm correspondence table?. ? dq/rdqs/wdqs/dm correspondence table 11. select area enable (sa) sa is used to support optional commands of mact, mpre and bref. refer to the ? command truth table?. sa can be tied to v ss if optional commands are not required. dq rdqs wdqs dm dq[7:0] rdqs0 wdqs0 dm0 dq[15:8] dm1 dq[23:16] rdqs1 wdqs1 dm2 dq[31:24] dm3 dq[39:32] rdqs2 wdqs2 dm4 dq[47:40] dm5 dq[55:48] rdqs3 wdqs3 dm6 dq[63:56] dm7
mb81eds516545 ds05-11463-2e 7 block diagram v dd v ss ck cke command decoder clock buffer address buffer i/o buffer mode register ras cas we cs to each block memory core controller ba[1:0] address countroller v ssq v ddq a[12:0] ck sa memory cell array (2 m bit 64) x controller read amp write amp bus controller bank0 bank1 bank2 bank3 y controller burst countroller rdqs[3:0] dm[7:0] wdqs[3:0] dq[63:0]
mb81eds516545 8 ds05-11463-2e simplified state diagram mode register set self refresh idle bank active auto refresh power down write power on precharge read write with auto precharge read with auto precharge writ read writ mrs self selfx ref act pd pdx pd reada writa pre pre power applied manual input automatic sequence writa reada pdx note: ? simplified state diagram? is ba sed on the single bank operation. state transition of multi bank oper ation are not described in all detail. deep power down dpdx dpd bst read bst active power down pre pre
mb81eds516545 ds05-11463-2e 9 functional description 1. power up initialization this device internal condition after power-up will be undefined. the following power up initialization sequence must be performed to start proper device operation. 1. apply power (v dd should be applied before or in parallel with v ddq ) and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, a nd nop or desl condition for a minimum of 300 s. 3. precharge all banks by precharge (p re) or precharge all (pall) command. 4. assert minimum of 2 auto refresh (ref) commands. 5. program the mode register by mode register set (mrs) command. 6. program the extended mode register (1 ) by mode register set (mrs) command. 7. program the extended mode register (2 ) by mode register set (mrs) command. in addition, cke must be high to ensure that output is high-z state. the mode register and extended mode register (1) and extended mode register (2) can be set before 2 auto-refresh commands (ref). 2. mode register the mode register is used to configure the type of de vice function among optional features. this device has 3 mode registers, mode register, extended mode register (1) and extended mode register (2). mode registers can be programmed by mode regiser set (mrs) co mmand. refer to the ?mode register table? in ? functional description?.
mb81eds516545 10 ds05-11463-2e mode register table a 2 a 1 a 0 burst length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 reserved 2 4 8 16 reserved reserved reserved 0 1 0 1 0 1 0 1 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 000 cl bl mode register a 1 a 0 ba 0 a 12 a 11 00 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 address 00 extended mode register (1) a 1 a 0 a 11 00 extended mode register (1) 0 00 0 a 12 0 0 ba 0 1 00 0 0 extended mode register (2) a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 address 00 art extended mode register (2) a 1 a 0 a 12 a 11 00 a 2 a 1 a 0 additional rdqs toggle 0 0 0 0 0 0 1 1 0 1 0 1 0 clock 1 clock 2 clock 3 clock 00 00 0 ba 0 00 address mode register a 6 a 5 a 4 cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 reserved reserved 2 3 4 reserved reserved reserved 0 1 0 1 0 1 0 1 a 6 pre driver strength 0 1 fast slow a 5 driver strength 0 1 normal weak ds pds ba 1 0 ba 1 0 1 ba 1
mb81eds516545 ds05-11463-2e 11 3. burst length (bl) burst length (bl) is the number of word to be read or write as the result of a single read or write command. it can be set on 2, 4, 8, 16 words boundary through mode re gister. the burst type is sequ ential that is incremental decoding scheme within a boundary address to be determined by burst length. device internal address counter assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address ( = 0). burst length starting column address burst address sequence (hexadecimal) a 3 a 2 a 1 a 0 2 xxx0 0 - 1 xxx1 1 - 0 4 x x 0 0 0 - 1 - 2 - 3 x x 0 1 1 - 2 - 3 - 0 x x 1 0 2 - 3 - 0 - 1 x x 1 1 3 - 0 - 1 - 2 8 x 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 x 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 x 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 x 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 x 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 x 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 x 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 x 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 16 0000 0-1-2-3-4-5-6-7-8-9-a-b-c-d-e-f 0001 1-2-3-4-5-6-7-8-9-a-b-c-d-e-f-0 0010 2-3-4-5-6-7-8-9-a-b-c-d-e-f-0-1 0011 3-4-5-6-7-8-9-a-b-c-d-e-f-0-1-2 0100 4-5-6-7-8-9-a-b-c-d-e-f-0-1-2-3 0101 5-6-7-8-9-a-b-c-d-e-f-0-1-2-3-4 0110 6-7-8-9-a-b-c-d-e-f-0-1-2-3-4-5 0111 7-8-9-a-b-c-d-e-f-0-1-2-3-4-5-6 1000 8-9-a-b-c-d-e-f-0-1-2-3-4-5-6-7 1001 9-a-b-c-d-e-f-0-1-2-3-4-5-6-7-8 1010 a-b-c-d-e-f-0-1-2-3-4-5-6-7-8-9 1011 b-c-d-e-f-0-1-2-3-4-5-6-7-8-9-a 1100 c-d-e-f-0-1-2-3-4-5-6-7-8-9-a-b 1101 d-e-f-0-1-2-3-4-5-6-7-8-9-a-b-c 1110 e-f-0-1-2-3-4-5-6-7-8-9-a-b-c-d 1111 f-0-1-2-3-4-5-6-7-8-9-a-b-c-d-e
mb81eds516545 12 ds05-11463-2e 4. cas latency (cl) cas latency (cl) is the delay betw een read command being registered and first read data becoming available during read operation. first read data will be valid after (cl-1) t ck + t ac from the ck rising edge where read command being latched. 5. driver strength (ds) driver strength (ds) is to adjust the driver strength of data output. 6. pre driver strength (pds) pre driver strength (pds) is to adjust the transition time of the data output without changing the output driver impedance. 7. additional rdqs toggle (art) additional rdqs toggle (art) is to set rdqs toggle co unt after the last pair of data output. total rdqs toggle count is bl/2 + art. rdqs timing with additional rd qs toggle (art) function @bl=4 dq (output) ck ck rdqs q0 q1 q2 q3 rdqs rdqs rdqs art = 0 art = 1 art = 2 art = 3 1 additional rdqs toggle 2 additional rdqs toggles 3 additional rdqs toggles
mb81eds516545 ds05-11463-2e 13 command truth table 1) basic command truth table note: v = valid, l = v il , h = v ih , x can be either v il or v ih , ra = row address, ca = column address all commands are assumed to be valid state transiti ons and latched on the rising edge of ck. cke assume to be kept high. *1: nop and desl commands have the same functionality. unless specifically noted, nop will represent both nop and desl command in later description. *2: when the current state is idle and cke=l, bst command will represent dpd command. refer to the ? cke command truth table?. *3: bst command can be applied to read or writ. r eada and writa must not be terminated by bst command. *4: read, reada, writ and writa commands can be i ssued after the corresponding bank has been activated by act or mact commands. refer to the ? simplified state diagram?. *5: act and mact command can be issued after corresp onding bank has been precharged by pre or pall or mpre command. refer to the ? simplified state diagram?. *6: sa must be high to issue optional co mmands of mact, mpre, bref and brefx. *7: ref command can be issued after all banks have be en precharged by pre or pall or mpre command. refer to the ? simplified state diagram?. *8: mrs command can be issued after all banks have been precharged and all dq are in high-z. mode register, extended mode register (1) and ext ended mode register (2) is selected through ba input. mode register, extended mode register (1) and ext ended mode register (2) must be set by mrs command after power up. command symbol cs ras cas we ba a10 (ap) a[9:0], a11, a12 sa deselect * 1 deslhxxxxx x l no operation * 1 nop l h h h x x x burst terminate * 2, * 3 bst l h h l x x x read * 3, * 4 readlhlhvl ca read with auto-precharge * 3, * 4 reada l h l h v h ca write * 3, * 4 writ l h l l v l ca write with auto-precharge * 3, * 4 writa l h l l v h ca bank active * 4, * 5 act l l h h v ra multi bank active * 4, * 5, * 6 mact l l h h v ra h precharge single bank * 5, * 7 pre l l h l v l x l precharge all banks * 5, * 7 pall l l h l x h x multi bank precharge * 5, * 6, * 7 mpre l l h l v l x h auto refresh * 7 ref l l l h x x x l background refresh entry * 6 bref l l l h v l v h background refresh exit * 6 brefx l l l h x h x mode register set * 8 mrs l l l l v v v l
mb81eds516545 14 ds05-11463-2e 2) cke command truth table note: v = valid, l = v il , h = v ih , x can be either v il or v ih *1: self and dpd commands can be is sued after all banks have been pr echarged and all dq are in high-z. *2: cke should be held high more than t refc period after selfx. command symbol cke cs ras cas we ba a [12:0] sa n-1 n self refresh entry * 1 selfhllllhx x l self refresh exit * 2 selfx l h lhhhx x hxxxx x power down entry * 1 pd h l lhhhx x hxxxx x power down exit pdx l h lhhhx x hxxxx x deep power down entry * 1 dpd h l l h h l x x deep power down exit dpdx l h lhhhx x hxxxx x
mb81eds516545 ds05-11463-2e 15 3) single bank operation (continued) current state cs ras cas we address command function idle hxxx x desl nop lhhh x nop l h h l x bst l h l h ba, ca, ap read/reada illegal * 1 l h l l ba, ca, ap writ/writa l l h h ba, ra act/mact bank active l l h l ba, ap pre/pall/ mpre nop * 2 l l l h x ref/bref auto refresh or background refresh * 3 llll mode mrs m ode register set * 3, * 4 bank active h x x x x desl nop lhhh x nop l h h l x bst l h l h ba, ca, ap read/reada start read; determine ap l h l l ba, ca, ap writ/writa start write; determine ap l l h h ba, ra act/mact illegal * 1 l l h l ba, ap pre/pall/ mpre precharge; determine precharge type l l l h x ref/bref illegal llll mode mrs
mb81eds516545 16 ds05-11463-2e (continued) current state cs ras cas we address command function read hxxx x desl nop lhhh x nop l h h l x bst burst terminate bank active l h l h ba, ca, ap read/reada interrupt burst read by new burst read; determine ap l h l l ba, ca, ap writ/writa illegal l l h h ba, ra act/mact illegal * 1 l l h l ba, ap pre/pall/ mpre terminate burst read by precharge idle l l l h x ref/bref illegal llll mode mrs write hxxx x desl nop lhhh x nop l h h l x bst burst terminate bank active l h l h ba, ca, ap read/reada interrupt burst write by new burst read; determine ap * 5 l h l l ba, ca, ap writ/writa interrupt burst write by new burst write; determine ap l l h h ba, ra act/mact illegal * 1 l l h l ba, ap pre/pall/ mpre l l l h x ref/bref illegal llll mode mrs
mb81eds516545 ds05-11463-2e 17 (continued) current state cs ras cas we address command function read with auto precharge hxxx x desl nop lhhh x nop l h h l x bst illegal l h l h ba, ca, ap read/reada illegal * 1 l h l l ba, ca, ap writ/writa l l h h ba, ra act/mact l l h l ba, ap pre/pall/ mpre l l l h x ref/bref illegal llll mode mrs write with auto pre- charge hxxx x desl nop lhhh x nop l h h l x bst illegal l h l h ba, ca, ap read/reada illegal * 1 l h l l ba, ca, ap writ/writa l l h h ba, ra act/mact l l h l ba, ap pre/pall/ mpre l l l h x ref/bref illegal llll mode mrs
mb81eds516545 18 ds05-11463-2e (continued) current state cs ras cas we address command function write recovering hxxx x desl nop lhhh x nop l h h l x bst l h l h ba, ca, ap read/reada illegal l h l l ba, ca, ap writ/writa start write; determine ap l l h h ba, ra act/mact illegal * 1 l l h l ba, ap pre/pall/ mpre l l l h x ref/bref illegal llll mode mrs precharging h x x x x desl nop lhhh x nop l h h l x bst illegal l h l h ba, ca, ap read/reada illegal * 1 l h l l ba, ca, ap writ/writa l l h h ba, ra act/mact l l h l ba, ap pre/pall/ mpre nop * 2 l l l h x ref/bref illegal llll mode mrs
mb81eds516545 ds05-11463-2e 19 (continued) ra = row address ba = bank address ca = column address ap = auto precharge note: assuming cke = h during the previous clock cycle and the current clock cycle. after illegal commands are asserted, following command and st ored data should not be guaranteed. *1: illegal to bank in the specified state. command entry ma y be legal depending on the state of bank selected by ba. *2: nop to bank in precharging or in idle state. bank in active state may be precharged depending on ba. *3: illegal if any bank is not idle. *4: mrs command should be issued on c ondition that all dq are in high-z. *5: requires appropriate dm masking. current state cs ras cas we address command function bank activating hxxx x desl nop lhhh x nop l h h l x bst illegal * 2 l h l h ba, ca, ap read/reada l h l l ba, ca, ap writ/writa l l h h ba, ra act/mact l l h l ba, ap pre/pall/ mpre l l l h x ref/self/bref illegal llll mode mrs refreshing/ mode register setting hxxx x desl nop lhhh x nop l h h l x bst illegal lhlx x read/reada/ writ/writa llxx x act/mact/pre/ pall/mpre/ ref/self/ bref/mrs
mb81eds516545 20 ds05-11463-2e bank operation command table minimum clock latency or delay time for single bank operation ? - ? : illegal *1: assume all banks are in idle state. *2: assume output is in high-z state. *3: assume t ras (min.) is satisfied. *4: act to reada interval must be longer than t ras - bl/2. *5: act to writa interval must be longer than t ras - (1 + bl/2 + t wr ). *6: assume appropriate dm masking. *7: 1st read or write access must be allowed for appropr iate bank specified in the act and mact commands of ? command truth table?. *8: brefx command can be issued only when background refresh is in progress. 2nd command (same bank) mrs act read reada writ writa bst pre pall ref self mact mpre bref brefx 1st command mrs t mrd t mrd ? ? ? ? t mrd t mrd t mrd t mrd t mrd t mrd t mrd t mrd ? act ? ? t rcd *4 t rcd t rcd *5 t rcd ? t ras t ras ? ? ? t ras ? ? read ? ? 11 *6 bl/2 +cl *6 bl/2 +cl 1 *3 1 *3 1 ? ? ? *3 1 ? ? reada *1, *2 bl/2 + t rp bl/2 + t rp ? ? ? ? bl/2 + t rp bl/2 + t rp bl/2 + t rp *1 bl/2 + t rp *1, *2 bl/2 + t rp bl/2 + t rp bl/2 + t rp bl/2 + t rp ? writ ? ? *6 2 + t wtr *6 2 + t wtr 111 *3 bl/2 + 1 + t wr *3 bl/2 + 1 + t wr ? ? ? *3 bl/2 + 1 + t wr ? ? writa *1, *2 bl/2 + 1 + t dal bl/2 + 1 + t dal ? ? ? ? bl/2 +1 + t dal bl/2 +1 + t dal bl/2 +1 + t dal *1 bl/2 +1 + t dal *1, *2 bl/2 +1 + t dal bl/2 + 1 + t dal bl/2 +1 + t dal bl/2 +1 + t dal ? read - bst ? ? 1 1 cl cl 1 *3 1 *3 1 ? ? ? 1 ? ? writ - bst ? ? 1 + t wtr 1 + t wtr 11 *3 1 + t wr *3 1 + t wr ? ? ? 1 + t wr ? ? pre *1, *2 t rp t rp ? ? ? ? t rp 11 *1 t rp *1, *2 t rp t rp 1t rp ? pall *2 t rp t rp ? ? ? ? t rp 11t rp *2 t rp t rp 1t rp ? ref t refc t refc ? ? ? ? t refc t refc t refc t refc t refc t refc t refc t refc ? selfx t refc t refc ? ? ? ? t refc t refc t refc t refc t refc t refc t refc t refc ? mact ? ? *7 t rcd *7 t rcd *7 t rcd *7 t rcd ? t ras 1 + t ras ? ? ? 1 + t ras ? ? mpre *1, *2 t rp t rp ? ? ? ? t rp 11 *1 t rp *1, *2 t rp t rp 1t rp ? bref rc x t refc rc x t refc ? ? ? ? ? rc x t refc rc x t refc rc x t refc rc x t refc rc x t refc rc x t refc rc x t refc *8 t refc brefx t refc t refc ? ? ? ? t refc t refc t refc t refc t refc t refc t refc t refc ?
mb81eds516545 ds05-11463-2e 21 minimum clock latency or delay time for multi bank operation ? - ? : illegal *1: assume other bank is in idle state. *2: assume output is in high-z state. *3: assume t rrd is satisfied. *4: assume t ras is satisfied. *5: assume appropriate dm masking. *6: 1st read or write access must be allowed for appropr iate bank specified in the act and mact commands of ? command truth table?. *7: brefx command can be issued only when background refresh is in progress. 2nd command (other bank) mrs act read reada writ writa bst pre pall ref self mact mpre bref brefx 1st command mrs t mrd t mrd ? ? ? ? t mrd t mrd t mrd t mrd t mrd t mrd t mrd t mrd ? act ? t rrd 111111t ras ? ? t rrd 1t rrd *7 t rrd read ? *1, *3 1 11 *5 bl/2 +cl *5 bl/2 +cl 11 *4 1 ? ? *1, *3 1 11 *7 1 reada *1, *2 bl/2 + t rp *1, *3 1 bl/2 bl/2 *5 bl/2 +cl *5 bl/2 +cl bl/2 + t rp 1 *4 bl/2 + t rp *1 bl/2 + t rp *1 bl/2 + t rp *1, *3 1 11 *7 1 writ ? *1, *3 1 *5 2 + t wtr *5 2 + t wtr 1111 *4 bl/2 + 1 + t wr ? ? *1, *3 1 11 *7 1 writa *1 bl/2 + 1 + t dal *1, *3 1 *5 bl/2 + 1 + t wtr *5 bl/2 + 1 + t wtr bl/2 bl/2 bl/2 +1 + t dal 1 *4 bl/2 + 1 + t dal *1 bl/2 + 1 + t dal *1 bl/2 + 1 + t dal *1, *3 1 11 *7 1 read - bst ? *1, *3 1 1 1 cl cl 1 1 *4 1 ? ? *1, *3 1 11 *7 1 writ - bst ? 1 + t wtr 1 + t wtr 11 1 *4 1 + t wr ? ? pre *1, *2 t rp *1, *3 1 1111111 *1 t rp *1, *2 t rp *1, *3 1 11 *7 1 pall *1 t rp t rp ? ? ? ? t rp 11t rp t rp t rp 1t rp ? ref t refc t refc ? ? ? ? t refc t refc t refc t refc t refc t refc t refc t refc ? selfx t refc t refc ? ? ? ? t refc t refc t refc t refc t refc t refc t refc t refc ? mact ? t rrd *6 1 *6 1 *6 1 *6 1 111+ t ras ? ? t rrd 1t rrd *7 t rrd mpre *1, *2 t rp *1, *3 1 1111111 *1 t rp *1, *2 t rp *1, *3 1 11 *7 1 bref rc x t refc t rrd 111111 rc x t refc rc x t refc rc x t refc t rrd 1 rc x t refc *7 t refc brefx t refc t rrd 111111t refc t refc t refc t rrd 1t refc ?
mb81eds516545 22 ds05-11463-2e command description 1. deselect (desl) when cs is high at the ck rising edge, all input signals are neglected. internal operation such as burst cycle is held. 2. no operation (nop) nop disables address and data input and internal operation such as burst cycle is held. 3. bank active (act) act activates the bank selected by ba and la tch the row address through a0 to a12. 4. read (read) read initiates burst read operation to an activated row address. address inputs of a[7:0] determine starting column address and a10 determines whether auto precha rge is used or not. initially rdqs output low level then start toggling together with data output with resp ect to cl and bl. the read data output is edge-aligned with first rising edge of rdqs and successive read da ta output are edge-aligned to the successive edge of rdqs. the ck drives the rising edge of rdqs and even data, and the ck drives the falling edge of rdqs and odd data.
mb81eds516545 ds05-11463-2e 23 5. read with auto precharge (reada) reada commands can be issued by read command with ap (a10) = h. au to precharge is a feature which precharge the activated bank after the co mpletion of burst read operation. the t ras is defined from between active (act) command to the internal precharge which starts after bl/2 from reada command. read with auto precharge operation should not be interrupted by subsequent read, reada, write, writea commands. next active (act) command ca n be issued after bl/2 + t rp after reada command. t ac t lz t lz ck dq rdqs ck t dqsck t qh t qh t ac t ac t dqsq t dqsq t dqsck dq rdqs t dqsck t qh t qh t dqsq t dqsq q even q even t dqsck t ac (max.) t ac (min.) q even q odd t ac q odd command read cas latency q odd nop
mb81eds516545 24 ds05-11463-2e 6. write (writ) writ initiates burst write operation to an active row addr ess. address inputs of a[7:0] determine starting column address and ap(a10) determines whet her auto precharge is used or not. wdqs input must be provided in order to latch the input data. wdqs mu st be brought to low to satisfy the specified time duration of the write preamble setup time to ck (t wpres ). input data window must be guaranteed with specified minimum setup and hold time against edge of wdqs input (t ds , t dh ). the input data appearing on dq is written into memory cell array subject to the dm input logic level appearing coin cident with the input data. if a given signal on dm is registered low, the corresponding data will be written into th e cell array. and if a given signal on dm is registered high, the corresponding data will be masked and write will not be executed to that byte. after data input with respect to bl is completed, wdqs must be kept low for the specified minimum value of write postamble time (t wpst ). t wpst t ds t dh t ds t dh t ds t ds ck dq wdqs ck t ds t dqss t dh t dqsh t dqsl t ds t dh t ds t dh t ds t dh dm t ds t dh t ds t dh t wpst t dss t dsh dq wdqs t ds t dqss t dh t dqsh t dqsl t ds t dh t ds t dh t ds t dh dm t dh t ds t dh t dh t ds t dh t dss t dsh q even q odd mask q odd q even q odd mask q odd t wpres t wpres t dqss (min.) t dqss (max.) command writ t dss t dss nop
mb81eds516545 ds05-11463-2e 25 7. write with auto precharge (writa) writa commands can be issued by writ command with ap (a10) = h. auto precharge is a feature which precharge the activated bank after the completion of bu rst write operation. the t ras is defined from between active (act) command to the internal prec harge which starts after 1+ bl/2 + t wr from writa command. writ with auto precharge operation should not be interrupted by subsequent read, reada, writ, writa commands. next active (act) command can be issued after 1+ bl/2 + t dal after writa command. 8. burst terminate (bst) bst terminates the burst read or write operation. when a burst read is terminated by bst command, the data output will be in high-z after cas latency from the bst command. when a burst write is terminated by bst command, the data input after 1 cloc k from bst command will be masked. terminate read by bst @cl=3 terminate write by bst ck command dq (output) cl = 3 bst q0 q1 nop cl = 3 read nop ck command dq (input) masked by bst bst nop writ nop d0 d1 d2 d3 1 clock
mb81eds516545 26 ds05-11463-2e 9. precharge single bank (pre) precharge single bank (pre) command starts precharge operation for a bank selected by ba. a selected bank will be in idle state after specified time duration of t rp from pre command. a10 determines whether one or all banks are precharged. if ap(a10) = l, a bank to be selected by ba is precharged. 10. precharge all bank (pall) precharge all banks (pall) command starts precharge operation for all banks. all banks will be in idle state after specified time duration of t rp from pall command. a10 determines whether one or all banks are precharged. if ap(a10) = h, all banks are pr echarged and ba input is a ?don't care?. 11. auto refresh (ref) auto refresh (ref) command starts internal refres h operation which uses the internal refresh address counter. all banks must be precharged prior to the auto-refresh command. data retention capability depends on the junction temperature (tj). total 8,192 auto refresh (ref) commands must be asserted within the following refresh period of t ref . 12. self-refresh entry (self) self refresh entry (self) commands can be issued by auto refresh (ref) command in conjunction with cke = low after last read da ta has been appeared on dq. during self refresh mode, stored data can be retained without external clocking and all inputs except for cke will be a ?don't care ?. self refresh mode can be used when tj is less than + 85 c. auto refresh must be issued to retain data when tj is greater than + 85 c. 13. self-refresh exit (selfx) to exit self-refresh mode, apply minimum t is after cke brought high, and then the no operation command (nop) or the deselect command (desl) should be asserted within one t refc period. cke should be held high within one t refc period after t is . refer to the ?(15) self refresh entry and exit? in ? timing diagrams? for the detail. it is recommended to assert an auto-refresh command just after the t refc period to avoid the violation of refresh period. 14. mode register set (mrs) mode register set (mrs) commands to program the mode registers. once a mode register is programmed, the contents of the register will be held until re-p rogrammed by another mrs command. mrs command should only be issued on conditions that all dqs are in high-z an d all banks are in idle state. the contents of the mode registers is undefined after the powe r-up and deep power down exit. ther efore mrs must be issued to set each content of mode registers after initialization. refer to the ?power up initialization? in ? functional description?. 15. power down entry (pd) power down entry (pd) commands to drive the devi ce in power down mode and maintains low power state as long as cke is kept low. during power down st ate, all inputs signals are a ?don't care? except for cke. power down mode must be entered on co ndition that all dqs are in high-z. 16. power down exit (pdx) power down exit (pdx) commands to resume the device from power down mode. any commands can be detected 1 clock after pdx commands. tj max ( c) t ref (ms) + 105 64 + 125 16.7
mb81eds516545 ds05-11463-2e 27 17. deep power down entry (dpd) deep power down entry (dpd) commands to drive the de vice in deep power down mode which is the lowest power consumption but all stored data and the co ntents of mode registers will be lost. during deep power down state, all inputs signals except for cke are a ?don 't care? and all dqs and rdqs will be in high-z. deep power down mode must be entered on conditions that all dqs are in high- z and all banks are in idle state. 18. deep power down exit (dpdx) deep power down exit (dpdx) commands to resume the device from deep power down mode. power up initialization procedure must be performed after dpdx commands. refer to the ?power up initialization? in ? functional description?. 19. multi bank active (mact) multi bank active (mact) command activates 2 banks simu ltaneously selected by ba1. sa must be high to issue mact command. ba1 determines the target bank gr oup is either bank 0 & 1 or bank 2 & 3. and ba0 determines the bank where 1st read or write access can be performed. if mact command is issued to bank 0 (or bank 2) with ra = n, same row address of ra = n is activated for bank 1 (or bank 3) and 1st read or write access must be allowed for ra=n of bank 0 (or bank 2) . if mact command is issued to bank 1 (or bank 3) with ra = n, next row address of ra = n + 1 is activa ted for bank 0 (or bank 2) and 1st read or write access must be allowed for ra = n of bank 1 (or bank 3). if ma ct command is issued to bank 1 (or bank 3) with ra = fffh, internal row address counter is wrap around therefor e activated row address is fffh for bank 1 (or bank 3) and 000h for bank 0 (or bank 2). command truth table of act and mact the following memory map example enables to issue effective mact command for 2-bank interleave access between bank 0 and bank 1 or bank 2 and bank 3. memory map example for 2-bank in terleave access by mact command command symbol sa ba1 ba0 row address a[12:0] 1st access 2nd access bank ra bank ra bank active act l ll ra = n bank 0 ra = n na l h bank 1 ra = n na h l bank 2 ra = n na h h bank 3 ra = n na multi bank active mact h ll ra = n bank 0 ra = n bank 1 ra = n l h bank 1 ra = n bank 0 ra = n + 1 h l bank 2 ra = n bank 3 ra = n h h bank 3 ra = n bank 2 ra = n + 1 bank 0101 010101 0101 ra 000h 001h n - 1 n n + 1 fffh fffh bank 2323 232323 2323 ra 000h 001h n - 1 n n + 1 fffh fffh
mb81eds516545 28 ds05-11463-2e 20. multi bank precharge (mpre) multi bank precharge (mpre) command starts prec harge operation for 2 banks selected by ba1. sa must be high to issue mpre command. se lected 2 banks will be in idle stat e after specified time duration of t rp from mpre command. ba1 determines whether the target bank group is bank 0 & 1 or bank 2 & 3. if mpre command is issued to ba1 = l, bank 0 and bank 1 will be precharged simultaneously. if mpre command is issued to ba1 = h, bank 2 and bank 3 will be precharged simultaneously. command truth table of pre, pall and mpre 21. background refresh entry (bref) background refresh entry (bref) command starts in ternal refresh operation for 2 banks selected by ba1. sa must be high to issue bref command and a 10 determines either background refresh entry (bref) or exit (brefx). 2 banks which will be refres hed must be precharged prior to the bref command. when bref command is issued, refresh count (rc) must be set through a[9:0] inputs as shown in the following table. rc defines how many refresh cycle is execut ed by one bref command. rc can be set from 1 to 31 cycles. refreshed banks will be in refresh state for a period specified by rc x t refc . while any read and write access must not be performed during auto refresh whic h initiates all banks refresh, background refresh can allow to read or write access to 2 b anks which are not refreshed. ba1 deter mines the target bank group either bank 0 & 1 or bank 2 & 3. if bref command is issued to ba1 = l, ba nk 0 & 1 will be refreshed and bank 2 & 3 can be accessible. if bref command is issued to ba1 = h, bank 2 & 3 will be refreshed and bank 0 & 1 can be accessible. 8,192 bref command must be asserted to both bank group of bank 0 & 1 and bank 2 & 3 within the refresh period of t ref . when background refresh is in progress for one bank group, bref command must not be issue to the other bank group. 22. background refresh exit (brefx) background refresh exit (brefx) command terminates internal refresh operation for 2 banks initiated by bref command for a period of rc x t refc . sa must be high to issue br efx command. 2 banks will be idle state after t refc from brefx command. brefx command can be issu ed when background refresh is in progress. command symbol cs ras cas we ba1 ba0 a10 (ap) a[9:0], a11, a12 sa precharged bank precharge single bank pre llhl ll l x l bank 0 l h bank 1 h l bank 2 h h bank 3 precharge all bank pall x x h all banks multi bank precharge mpre l xl h bank 0 & 1 hbank 2 & 3
mb81eds516545 ds05-11463-2e 29 command truth table of bref and brefx command symbol cs ras cas we ba1 ba0 a10 (ap) a[9:0], a11, a12 sa refreshed bank auto refresh ref lllh xxx x l all banks background refresh entry bref l xl v (rc) h bank 0 & 1 hbank 2 & 3 background refresh exit brefx x x h x h bank 0 & 1 bank 2 & 3
mb81eds516545 30 ds05-11463-2e refresh count (rc) definition table * : a[12:0] = 000h must not be set for rc. refresh count (rc) a10 a[5:9], a11, a12 a4 a3 a2 a1 a0 illegal* ll l l l l l 1 h 2 h l 3 h 4 h l l 5 h 6 h l 7 h 8 h l l l 9 h 10 h l 11 h 12 h l l 13 h 14 h l 15 h 16 h l l l l 17 h 18 h l 19 h 20 h l l 21 h 22 h l 23 h 24 h l l l 25 h 26 h l 27 h 28 h l l 29 h 30 h l 31 h
mb81eds516545 ds05-11463-2e 31 absolute maximum ratings warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. recommended operating conditions *1: v ddq must be less than or equal to v dd . *2: maximum dc voltage on input or i/o pins is v ddq + 0.3 v. during voltage transitions, inputs may positive overshoot to v ddq + 1.0v for periods of up to 3 ns. *3: minimum dc voltage on input or i/o pins is -0.3 v. during voltage transitions, inputs may negative overshoot to v ssq - 1.0v for periods of up to 3 ns. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. capacitance (t a = + 25 c, f = 1 mhz) parameter symbol rating unit supply voltage relative to v ss v dd ,v ddq -0.5 to +2.3 v input / output voltage relative to v ss v in , v out -0.5 to +2.3 v short circuit output current i out 50 ma power dissipation p d 1.0 w storage temperature t stg -55 to +125 c parameter symbol min. typ. max. unit supply voltage *1 v dd , v ddq 1.7 1.8 1.9 v v ss , v ssq 000 v dc input high voltage *2 v ih (dc) v ddq 0.7 ? v ddq + 0.3 v ac input high voltage *2 v ih (ac) v ddq 0.8 ? v ddq + 0.3 v dc input low voltage *3 v il (dc) -0.3 ? v ddq 0.3 v ac input low voltage *3 v il (ac) -0.3 ? v ddq 0.2 v junction temperature t j -10 ? +125 c parameter symbol min. typ. max. unit input capacitance, except for wdqs, dm c in1 1 ? 2.5 pf input capacitance for wdqs, dm c in2 2 ? 4pf i/o capacitance c i/o 2 ? 4pf
mb81eds516545 32 ds05-11463-2e electrical characteristics 1. dc characteristics (under recommended operating c onditions unless otherwise noted) (continued) parameter symbol condition value unit min. max. output high voltage v oh(dc) i oh = -0.1 ma v ddq ? 0.2 ? v output low voltage v ol(dc) i ol = 0.1 ma ? 0.2 v input leakage cur- rent i li 0 v v in v ddq , all other pins not under test = 0 v ? 55 a output leakage cur- rent i lo 0 v v in v ddq , data out disabled ? 55 a operating one bank active-precharge current i dd0 t rc = t rc min, t ck = t ck min, cke = v ih , cs = v ih addresses inputs are switching; data bus inputs are stable tj + 105 c ? 65 ma tj + 125 c ? 75 ma precharge standby current i dd2p all banks idle, cke = v il , cs = v ih , t ck = t ck min, address and control inputs are switching; data bus inputs are stable tj + 105 c ? 6 ma tj + 125 c ? 9 i dd2n all banks idle, cke = v ih , cs = v ih , t ck = t ck min, address and control inputs are switching; data bus inputs are stable tj + 105 c ? 15 ma tj + 125 c ? 20 ma operating burst read current i dd4r one bank active, bl = 4, t ck = t ck min, output pin open, gapless data, address inputs are switching; 50% data change each burst transfer ? 300 ma operating burst write current i dd4w one bank active, bl = 4, t ck = t ck min, gapless data, address inputs are switching; 50% data change each burst transfer ? 380 ma auto refresh current i dd5 t rc = t rfc min, t ck = t ck min, cke = v ih , address and control inputs are switching; data bus inputs are stable ? 120 ma
mb81eds516545 ds05-11463-2e 33 (continued) notes: ? all voltages are referenced to v ss . ? after power on, initialization following power-up timi ng is required. dc characteristics are guaranteed after the initialization. ?i dd depends on the output terminat ion or load condition, clock cycle rate, signal clocking rate. the specified values are obtained with the output open condition. parameter symbol condition value unit min. max. self refresh current i dd6 cke = v il , cs = v il , address and control inputs are stable; data bus inputs are stable ? 6ma deep power down current i dd8 address and control inputs are stable; data bus inputs are stable ? 300 a
mb81eds516545 34 ds05-11463-2e 2. ac characteristics (under recommended operating c onditions unless otherwise noted) *1, *2 (continued) parameter symbol value unit min. max. dq output access time from ck/ck (t ck = t ck min)* 3, * 4, * 5, * 7 t ac 26ns rdqs output access time from ck/ck * 3, * 4, * 5 t dqsck 26ns clock high level width * 3 t ch 2 ? ns clock low level width * 3 t cl 2 ? ns delay between ck and ck * 4 t dc 0.45 0.55 t ck clock cycle time cl = 2 t ck 15 ? ns cl = 3 7.4 cl = 4 tj + 105 c4.6 tj + 125 c5 dq and dm input setup time* 3 tj + 105 c t ds 0.4 ? ns tj + 125 c0.5 ? ns dq and dm input hold time* 3 tj + 105 c t dh 0.4 ? ns tj + 125 c0.5 ? ns dq and dm input pulse width t dipw 0.35 ? t ck address and control input setup time * 3 t is 0.9 ? ns address and control input hold time * 3 t ih 0.9 ? ns address and control input pulse width t ipw 0.6 ? t ck dq low-z time from ck/ck * 3, * 5 t lz 0 ? ns dq high-z time from ck/ck * 3, * 5, * 6 t hz ? 6ns rdqs to dq skew * 4 t dqsq ? 0.4 ns dq output hold time from rdqs * 3, * 4 t qh t dc ? 0.5 ? ns writ command to 1st wd qs latching transition t dqss 0.75 1.25 t ck wdqs input high level width t dqsh 0.35 ? t ck wdqs input low level width t dqsl 0.35 ? t ck wdqs falling edge to ck setup time t dss 0.2 ? t ck wdqs falling edge hold time from ck t dsh 0.2 ? t ck mrs command period t mrd 2 ? t ck write preamble setup time t wpres 0 ? ns write postamble time t wpst 1 ? t ck
mb81eds516545 ds05-11463-2e 35 (continued) (under recommended operating c onditions unless otherwise noted) *1, *2 * 1: ac characteristics are measured after the power up initialization procedure. * 2: v dd 0.5 is the reference level for 1.8 v i/o fo r measuring timing of input/output signals. * 3: if input signal transition time (t t ) is longer than 1 ns; [(t t /2) ? 0.5] ns should be added to t ac (max), t dqsck (max) and t hz (max) spec values, [(t t /2) ? 0.5] ns should be subtracted from t lz (min) and t qh (min) spec values, and (t t - 1.0) ns should be added to t ch (min), t cl (min), t is (min), t ih (min), t ds (min) and t dh (min) spec values. * 4: the data valid window is defined as t qh - t dqsq . the data valid window depends on t dc which is defined between rising edge of ck and rising edge of ck . the data valid window is guaranteed when t dc is satisfied. * 5: t ac , t dqsck , t lz and t hz , are measured under output load circuit sh own in ? 3. measurement condition of ac characteristics? in ? elecrtrical characteristics? and driver strength (ds) = normal, pre driver strength (pds) = fast are assumed. * 6: specified where output buffer is no longer driven. * 7: the sum of actual clock count of t ras and t rp must be equal or greater than specified minimum t rc . * 8: t rrd is applied to act (mact) to bref, act (mact) to brefx, bref to act (mact) and brefx to act (mact). refer to the ? bank operation command table?. * 9: this value is for reference only. * 10: transition times are measured between v ih (ac) min and v il (ac) max. parameter symbol value unit min. max. act to pre, mpre, pall command period * 7 t ras 37 8000 ns act, mact to act, mact command period (same bank) * 7 t rc 59.2 ? ns ref to act, ref command period t refc 100 ? ns act to read or writ command period t rcd 20 ? ns precharge period * 7 t rp 18 ? ns act, mact to act, mact command period (other bank)* 8 t rrd 9.2 ? ns write recovery time t wr 12 ? ns data input to act, ref command period cl = 2 t dal 1 clk + t rp ? ns cl = 3 2 clk + t rp cl = 4 3 clk + t rp internal write to read command delay t wtr 9.2 ? ns average refresh period * 9 tj + 105 c t refi ? 7.8 s tj + 125 c2.0 average periodic refresh interval tj + 105 c t ref ? 64 ms tj + 125 c16.7 transition time* 10 t t ? 1ns
mb81eds516545 36 ds05-11463-2e 3. measurement condition of ac characteristics device under test v dd v dd 0.5 v v ss out 0.1 f 10 pf 50
mb81eds516545 ds05-11463-2e 37 timing diagrams (1) read* (assuming cl = 4, bl = 8) * : ra = row address, ba = bank address, ca = column address, ap = auto precharge ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h ra ra ca ba ba ra ba ba q0 act pre t rcd t rp t rc t ras q1 q3 q2 q5 q4 q7 q6 read act ra address don?t care
mb81eds516545 38 ds05-11463-2e (2) read to read* 1 (assuming cl = 4, bl = 8) *1: ra = row address, ba = bank address, ca = column address, ap = auto precharge *2: previous burst read can be in terrupted by subsequent burst read. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h ra ra ra ra n n 010 0 11 q0 t rcd cl = 4 cl = 4 t rcd q1 q3 q2 q0 q1 q3 q2 q1 q0 q1 q0 q3 q2 q5 q4 q7 q6 mm cl = 4 cl = 4 address read * 2 bank 0, ca = n don?t care read * 2 bank 1, ca = n read * 2 bank 1, ca = m read bank 0, ca = m act bank 0 act bank 1
mb81eds516545 ds05-11463-2e 39 (3) read to precharge * 1 (assuming cl = 4, bl = 8) *1: ra = row address, ba = bank address, ca = column address, ap = auto precharge *2: burst read operation can be term inated by pre command. all dq pins become high-z after cl from pre command. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h ra ba ba ra ra ra ca ca act act pre t rcd cl = 4t rcd cl = 4 cl = 4 *2 q0 q1 q0 q1 q3 q2 read pre *2 read ba ba ba ba t ras t ras t rp t rc address don?t care
mb81eds516545 40 ds05-11463-2e (4) read with auto-precharge * 1 (assuming cl = 4, bl = 8) *1: ra = row address, ba = bank address, ca = column address, ap = auto precharge *2: internal precharge operation starts after bl/2 from reada command. t ras must be satisfied. *3: next act command can be issued after bl/2 + t rp from reada command. t rc must be satisfied. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h ra ra ca ba ba ra ba q2 act start * 2 t rcd t rp t rc t ras q3 q0 q1 q5 q4 q7 q6 reada precharge act * 3 ra bl/2 address don?t care
mb81eds516545 ds05-11463-2e 41 (5) write * 1 (assuming bl = 8) *1: ra = row address, ba = bank address, ca = column address, ap = auto precharge *2: burst write operation should not be terminated by pre command. pre can be issued after 1 + bl/2 + t wr from writ command. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h l ra ra ca ba ba ra ba ba d0 act pre* 2 t rcd t wr t rp t rc t ras d1 d3 d2 d5 d4 d7 d6 writ act ra address don?t care
mb81eds516545 42 ds05-11463-2e (6) write to write * 1 (assuming bl = 8) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : previous burst write can be interrupted by subsequent burst write. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h ra ra n 0 nm l m ra ra 0 1 1 0 1 t rcd t rcd d1 d0 d3 d2 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 d5 d4 d7 d6 d1 d0 d3 d2 address writ bank 0, ca = n don?t care writ* 2 bank 1, ca = n act bank 1 act bank 0 writ* 2 bank 1, ca = m writ bank 0, ca = m
mb81eds516545 ds05-11463-2e 43 (7) write with auto-precharge * 1 (assuming bl = 8) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : next act command can be issued after 1 + bl/2 + t dal (min) from writa command. t rc must be satisfied. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h ra ra ca ba ba ra ra ba l act *2 writa act precharge start t rcd t rc t ras t dal 1 + bl/2 d1 d0 d3 d2 d5 d4 d7 d6 address don?t care
mb81eds516545 44 ds05-11463-2e (8) read to write * 1 (assuming cl = 4, bl = 8) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : writ command can be issued after cl + bl/2 after read command. ck cke ck we ba ba h ra ba ba ap sa dm rdqs wdqs dq cs ras cas ra ca ca q1 q0 q3 q2 q5 q4 q7 q6 d1 d0 d3 d2 d5 d4 d7 d6 t rcd act read writ cl + bl/2 *2 address don?t care
mb81eds516545 ds05-11463-2e 45 (9) read to write with bst command * 1 (assuming cl = 4, bl = 8) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : writ command can be issued after cl from burst read termination by bst command. ck cke ck we ba ba h ra ba ba ap sa dm rdqs wdqs dq cs ras cas ra ca ca q1 q0 d1 d0 d3 d2 d5 d4 d7 d6 t rcd act read bst writ cl *2 address don?t care
mb81eds516545 46 ds05-11463-2e (10) write to read * 1 (assuming cl = 4, bl = 4) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : read command can be issued after 1 + bl/2 + t wtr from writ command. ck cke ck we ba ba h ra ba ba ap sa dm rdqs wdqs dq cs ras cas ra ca ca t rcd act read writ cl q1 q0 q3 q2 d1 d0 d3 d2 1 + bl/2 *2 t wtr address don?t care
mb81eds516545 ds05-11463-2e 47 (11) write to read with bst command * 1 (assuming cl = 4, bl = 8) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : the data input after 1 clock from bst command will be masked. *3 : read command can be issued after 1 + t wtr from burst write termination by bst command. ck cke ck we ba ba h ra ba ba ap sa dm rdqs wdqs dq cs ras cas ra ca ca q1 q0 q3 q2 q5 q4 q7 q6 t rcd act bst read *3 writ cl d1 d0 1 + t wtr address don?t care masked by bst *2
mb81eds516545 48 ds05-11463-2e (12) write to read with dm mask * 1 (assuming cl=4, bl = 8) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : dm must be high during t wtr from last pair of input data. ck cke ck we ba ba h ra ba ba ap sa dm rdqs wdqs dq cs ras cas ra ca ca q1 q0 q3 q2 q5 q4 q7 q6 t rcd act read writ cl d1 d0 t wtr address don?t care masked *2
mb81eds516545 ds05-11463-2e 49 (13) dm control write * 1 (assuming bl = 8) *1 : ra = row address, ba = bank address, ca = column address, ap = auto precharge *2 : when dm is registered high, t he corresponding data will be masked. ck cke cs we ras cas ap dm dq act writ pre act ba ck rdqs wdqs h sa ra ba ba ba ba ra ca ra ra t rp t rcd t ras t wr t rc l d1 d3 d5 d4 d7 d6 d0 address masked *2 don?t care
mb81eds516545 50 ds05-11463-2e (14) auto refresh * 1 *1 : ra = row address, ba = b ank address, ap = auto precharge *2 : all banks must be precharged pr ior to the auto refresh command (ref). *3 : either nop or desl command should be asserted during t refc period. *4 : act or mrs or ref command should be asserted after t refc from ref command. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa ra ra ba t rp t refc *3 act *4 pall *2 ref ref t refc *3 l h address don?t care
mb81eds516545 ds05-11463-2e 51 (15) self refresh entry and exit * 1 *1 : ra = row address, ba = b ank address, ap = auto precharge *2 : all banks must be precharged prior to self refresh entry (self) command. *3 : self refresh exit (selfx) command can be latched at the ck rising edge. *4 : either nop or desl co mmand can be used during t refc period. *5 : cke should be held high during t refc period after selfx command. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa l ra ra ba t is t rp t refc *4,*5 act pall *2 selfx *3 self address don?t care
mb81eds516545 52 ds05-11463-2e (16) mode register set* 1 *1 : ra = row address, ba = b ank address, ap = auto precharge *2 : mode register set (mrs) command must be asse rted after all banks have been precharged and all dq are in high-z. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa h ra ra ba l code code code code code code code code code t rp t refc t refc t mrd t mrd t mrd act pall * 2 mrs* 2 mrs* 2 ref ref mrs* 2 address don?t care
mb81eds516545 ds05-11463-2e 53 (17) power down entry and exit * 1 *1 : ra = row address, ba = b ank address, ap = auto precharge *2 : pd command can be issued after all dq are in high-z. *3 : act command can be issued after 1 cl ock from power down exit (pdx) command. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa ra ra ba high-z t is act *3 pall pdx pd *2 l address don?t care
mb81eds516545 54 ds05-11463-2e (18) deep power down entry* * : deep power down entry (dpd) command can be issued after all banks ha ve been precharged and all dq are in high-z. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa high-z t rp dpd pall address don?t care
mb81eds516545 ds05-11463-2e 55 (19) deep power down exit * 1 *1: ra = row address, ba = bank address, ap = auto precharge *2: power up initialization procedure mu st be performed after dpdx command. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs sa t is code ra ra ba code code code code code code code code high-z t rp t mrd t mrd t mrd t refc t refc 300 s act pall emrs ref dpdx *2 ref mrs emrs address don?t care
mb81eds516545 56 ds05-11463-2e (20) multi bank active to read to multi bank precharge* 1 (assuming cl = 4, bl = 4) *1: ra = row address, ba = bank address, ca = column address, ap = auto precharge *2: if mact command is issued to bank 0, 1st read co mmand must be issued to bank 0 followed by 2nd read command to bank 1. *3: if mact command is issued to bank 2, 1st read co mmand must be issued to bank 2 followed by 2nd read command to bank 3. t rrd t rcd t rcd cl *2 cl *2 cl *3 cl *3 t ras t ras q1 q0 q3 q2 q1 q0 q3 q2 q1 q0 q3 q2 q1 q0 q3 q2 ck cs we ras cas ap dm dq ba ck rdqs wdqs sa ra ra 0 ra ra 2 ca ca ca ca 01 23 02 address don?t care mact bank 2 & 3 mact bank 0 & 1 read* 2 bank 0 read* 2 bank 1 read* 3 bank 2 read* 3 bank 3 mpre bank 2 & 3 mpre bank 0 & 1
mb81eds516545 ds05-11463-2e 57 (21) multi bank active to write to multi bank precharge* 1 (assuming cl = 4, bl = 4) *1: ra = row address, ba = bank address, ca = column address, ap = auto precharge *2: if mact command is issued to b ank 0, 1st writ command must be i ssued to bank 0 followed by 2nd writ command to bank 1. *3: if mact command is issued to b ank 2, 1st writ command must be i ssued to bank 2 followed by 2nd writ command to bank 3. ck cs we ras cas ap dm dq ba ck rdqs wdqs sa ra ra 0 ra ra 2 ca ca ca ca 01230 2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 t rrd t rcd t rcd *2 *2 *3 *3 t wr t wr t ras t ras address don?t care mact * 3 bank 2 & 3 mact * 2 bank 0 & 1 writ * 2 bank 0 writ * 2 bank 1 writ * 3 bank 2 writ * 3 bank 3 mpre bank 2 & 3 mpre bank 0 & 1
mb81eds516545 58 ds05-11463-2e (22) background refresh entry and exit * 1 (assuming bl = 8) *1: ra = row address, ba = bank address, ca = column address, ap = auto precharge *2: refresh count (rc) must be set th rough a[9:0] together with bref command. *3: if mact command is issued to b ank 0, 1st writ command must be i ssued to bank 0 followed by 2nd writ command to bank 1. ck cke cs we ras cas ap dm dq ba ck rdqs wdqs h sa ra ra 0 ca ca rc *2 20 1 ra 2 t rrd t refc t rcd *3 *3 l d1 d3 d2 d5 d4 d7 d6 d0 d1 d2 d7 d6 d0 address bref bank 2 & 3 mact * 3 bank 0 & 1 writ * 3 bank 0 don?t care writ * 3 bank 1 mact bank 2 & 3 brefx bank 2 & 3
mb81eds516545 ds05-11463-2e 59 memo
mb81eds516545 fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/se rvices/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersi ble repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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